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Recent content by Yankie

  1. Y

    Configuration using $value$plusargs

    Hi, I want to have variable number of drivers for my verification env and also to have different configuration for each driver. Is there a way of doing it? E.g global_config class extends uvm_component; int no_of_drivers; int max_delay[]; function new(string name="gbl_cfg"...
  2. Y

    UVM Sequencer with a transfer function

    Hi, Is it possible to have a UVM sequencer that takes an object from UVM sequence and sends only a subset of the object to the driver? E.g class RECT extends uvm_sequence_item; int length, breadth, area, perimeter; endclass class CIR int radius; endclass class driver extends...
  3. Y

    Coverage for interface signals in UVM

    Hi, I have a question regarding coverage in UVM monitor. Presently, I have a base_test that extends from uvm_test. It directly creates the UVM monitor. The monitor reads the signals on the interface and pushes the read data in an internal mailbox. It does not have a TLM port. I want to cover...
  4. Y

    Porting of verilog assign/always@(*) statement to UVM

    Thanks Dave ! The interface is being used by many other modules. Also, the functionality of always@(*) is specific to my module. So I am less inclined towards moving always@(*) to the interface. The number of variables in always@(*) are just 3 or 4. However, these variables are being used in...
  5. Y

    Porting of verilog assign/always@(*) statement to UVM

    Hi, I am trying to port always@(*) blocks in my verilog environment to UVM. E.g always @ (*) begin a = tx_intf.A; b = ~a; end task gen; @(posedge clk); if(b) ----- @(posedge clk)...
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