Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi all;
I am trying to design a FD folded cascode (pmos input stage) op amp in cadence. When I look at in open loop, it's phase is ok, and the node voltages stay at their dc values. However when I make it closed loop via capacitive negative feedback the ac simulation gives the ac gain as...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.