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Recent content by xypxyp87

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    JTAG control issue of Bscan cell mode

    Re: JTAG control issue It has been fixed. In normal mode, TRSTL should be pull down
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    JTAG control issue of Bscan cell mode

    JTAG need insert Bscan cell between IO and core, but when JTAG is not used, how to control bscan cell mode, mode_1 signal, etc to normal mode? I have add pullup resistor to TDI TMS and TRST, but the mode and mode_1 are still X state at normal mode start time. Does is need a dedicated JTAG mode...
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    Can Tetramax convert VCDE to TSTL2 pattern?

    if no, which EDA tools can do this?
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    Does Ncsim support one task run on two or more cpu?

    ncsim two cpu If yes, how can I realize it?
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    does ncsim support one task run on two or more cpu?

    ncsim two cpu If does, how can I realize it?
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    ATPG in functional verification

    simulation evcd I have known that in some fabless company, they release their function pattern using VCD files, because the tester can convert VCD to relative format, such as Agilent Smartest PG. But many times the pattern cannot work well in tester. So in our company, we try to build a new...
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    ATPG in functional verification

    tmax atpg I have some questions to ask: What's your pattern format in functional verification? Is it VCD file?If isn't, how does your pattern generate? After pattern generation, do you run feedback simulation? And how can you do the test vector format conversion?
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    Synopsys Design Analyzer Problem !!

    After "design_analyzer & " command DA display OK. Don't use "file->read" menu to read files. You can open command window and use "read -f ....." command This maybe a bug in dc for linux. Or you can use design_vision. My dc version is 2003.03 (rh linux 9.0)

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