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Thanks @mrflibble for your help
I just needed the simulation to go right
Modulo 50 Counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity count64 is
Port ( clk : in STD_LOGIC;
enable : inout STD_LOGIC;
reset : in STD_LOGIC...
The counter resets after 24 seconds. It does not require to be so specific for outside reset/enable. I need something that works like a modulo-24 with 50 Hz input.
Can you assist me with how to "inform" the second counter?
Since I tried implementing the counter which goes to 50 as a COMPONENT...
So I wrote the code for both and they work perfectly separated.
Here it is for the Clock Generator counter that counts to 50 with a wait for 10000 us at the TestBench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity count64 is
Port ( clk : in STD_LOGIC...
On paper, I did that.
I have written both the codes separately and they work independently. But I am kind a newbie in VHDL and do not know how to "inform" (Clock signal = Enable) the second counter that the first one completed his count to 50
Yes I know. That is why I was talking about 2 counters at the beginning. Still tricky idea with the 11 bit counter. 8-)
I wrote the code for the 2 counters separately but I still do not know how to combine them so that the Clock Enable signal of the second one (modulo 24) will be dependent on...
Just one more thing I want to ask
Since I will need to display the passing seconds (1,2,3 ...) on a LED display, will they show between 1 Hertz apart or will the number be something like 50 after 1 second (since the counter is loaded with the value of 50 after 1 sec)?
If it is not, then I will...
Yeah I know what to do now. I was actually writing the code for 2 counters separately but now I see that only one is needed.
It can count both ways (up to down or vice versa) and then it resets/loads.
Thanks again you guys, I will post the code once I am finished (could take a while with all...
I need to count to 24 with a given 50 Hz clock signal (0.02 seconds). That is why I am using a 5-bit and 6-bit counter. And yes, I need to generate a pulse every second.
Nice idea with the 11-bit counter :grin: (5+6 haha).
So if I generate 1200 pulses on 50 Hz, I will theoretically get 24...
I'm beginner in VHDL and was asked to construct a 24 second counter with 50 Hz input. I designed it on paper with two counters, one modulo-24 counter using modulo-32 and the other is modulo-50 using modulo-64.
I started writing the codes for both separately. The first counts to 50 aka 1 second...
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