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Recent content by xun36

  1. X

    Layout: Any risk put two w<<L transistor close?

    So you mean if DRC is clean, it should work...?
  2. X

    Layout: Any risk put two w<<L transistor close?

    w/l transistor Hi, I have two or more transistors with W=0.5 L=50. I want to put them in the layout one by one aligned by their length. But in this case the the channels of two MOS gets very close. Is there any risk? Like the gate will reverse the Nwell to Ptype and make a short inbetween the...

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