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dick_freebird,
Thanks for your response.
You are saying 10-20% of Ron for whole wiring (chip, bond, leadframe). Here I only want to know
the parasitic metal(metal 1/2/3/4 and via) resistance because there kevin connection on the power
FET so bond and leadframe's voltage drop is common-mode...
I have a big power MOS FET and Ron is about 50m ohm. The routing metal wires (metal 1/2/3/4..and via ) on the layout
generate some parasitic resistance. I don't know how much the metal resistance could be.
Is 5 mohm good estimation? (In my case 5 mohm is about 10% of the power FET Ron: 50mohm...
caswtell, you method is very interesting way to evaluate the hysteretic converter. The whole loop is like a oscillator even though it's little bit
strange oscillator. It's not like the normal ring oscillator and it's more like a relaxation oscillator.
I agree with you that the loop gain...
I am working on a hysteretic buck regulator. I know this topology is always stable. But I have a question
about the open loop gain of this topology. Since the comparator is a non-linear circuit and I do not know
how to use linear model to represent this block. I just got a feeling that the loop...
I am going to design a project which uses SPI interface, which has 4 signals: SS* SCLK MISO MOSI. To my knowledge,
SS*, SCLK and MOSI are input singal and MISO is output signals. I have two questions:
1)
I am told the SPI is 25MHz. Is 25MHz too high for this SPI interface? What's the normal...
On my testbench there is a digital block (dig_ABC). This digital block (dig_ABC) has many logic gates and symbol view is used
for these gates on dig_ABC level. I want to use verilog view to run the simulation for the gates.
All of the gates are in one of my libraries, but there are only symbol...
If I have 3 analog blocks: AAA BBB CCC, AAA is toplevel block, BBB is inside AAA and CCC is inside BBB block, if
these is an analog signal called as xxx in CCC, now I want to monitor the xxx signal in another block (verilogams), how
to do this in verilogasm?
I know if they are digital, we can...
Does any one know which city has more analog ic companies/jobs:
Dallas ? Austin ?
How about salary level and living expense in the 2 cities?
Thank you!
I am wondering if someone here can briefly talk about the cities/areas in USA which have many IC companies, also the salary level/house price/living expense.
This will be very helpful for fresh graduates and working people who want to find
new job. Any input will be useful. Thank you!
If a circuit generates 100 output current, is there an easy way to model the output currents by using ONE statement other than these below.
I(out[1], gnd) <+ 5u;
I(out[2], gnd) <+ 5u;
I(out[3], gnd) <+ 5u;
I(out[4], gnd) <+ 5u;
I(out[5], gnd) <+ 5u;
...
...
I(out[100], gnd) <+ 5u;
...
JoannesPaulus,
I did not select the "Noise update" "step" option, does that mean the device noise is NOT included in the simulation results so the fft plots of
two cases (Cs=1pF and 4pF) and SNR values are almost same and does not reflect the real noise difference ? Thank you.
JoannesPaulus,
Thanks for your reply.
I did not select the "Noise update" "step" in my simulation. Should I select it? What' s the meaning of "Noise update" "step" ???
I designed a 2-1 sigma-delta modulator and found fft issue I don't understand. My sim has 2 steps:
1) run "tran" analysis in spectre (select "Transient Noise" option)
2) read data from modulator output to matlab and do fft in matlab
I used 2 different sampling capacitors (1pF, 4pF) for the...
I have 100us simulation result. If the startup part (say 0-5us) is not good and I don't want to plot it at all. I want to plot is from 5us-100us.
Is there any way to set the 5us-100us as a default option so that it can be plotted automatically each time after the simulation is done? Thank you!
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