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NEW SOC CHIP DEVELOPMENT FLOW
1.1 WHAT PRODUCTION
ACTIVITY:
Market information collection.
market analysis
People involved:
Market department(include customer support group)
Manager.
customer
1.2 Production function define include planning
Activity:
information collection.
Customer need...
set ow = `awk '/Author/ {print $2,$3,$4,$5}' ./tcase/$1/$1.v`
sed s/test_case/$1/g < transport_tb.v > $1\_tb.v
date >! temp1
set tm = `awk '{print $4"("$2"/"$3")"}' temp1`
I find these command in a shell script , what is the meaning?
I want to synthesizing the TOP module ,it has submodule U1 and also other submodule.
U1 is an analog module that don't need to be synthesized. But the property of U1 can affect other submodule when compile in DC. How to build model of U1.
usb idle vs. suspend
IDLE state for USB bus
suspend state for USB device and HOST
long IDLE state of USB bus may lead the suspend state of USB device and USB host.
When synthesizing TOP module in DC,U1 is a submodule in TOP.U1 is a IP from other vendor and have the spec document and a verilog behavioral description file that can’t be synthesized.Also the library file and db file can’t be get from the vendor.
More attribute of U1 is described in the...
The following is copied from synopsys.com
question is :
1)This program only find cells that connect to inout pins directly ,Is it enough and correct just only set_false_path with these cells.
2)From SOLD,just only four path exist ,input to output,input to FF/D,FF/clk to output and FF/CLK to...
create_generated_clock
create_generated_clock -name "PLL_CLK" -source [get_pins i_pll/CLK_REF}] -multiply_by 8 [get_pins {i_pll/CLK_OUT}]
the above command is executed with return value '1' in DC.
i_pll is a cell of the top design and it is a analog module,I just only read it's interface into...
clock jitter?
I think
The actual clock is not an ideal clock, it's period is not the same all the time.clock jitter represent the uncertainty of the actual clock frequency.
Re: buffers
1)when clock tree synthesis,buffer inserted to balance clock skew
2)to amply a signal for long path
to drive more load
3)to isolation macro module,buffer can be take as less load for that drive it and having much driven capacity for the module that it drive.
4) to fix hold...
//the following dc script resolved this problem.
define_design_lib work -path ./WORK
analyze -f verilog encrypt.v
analyze -f verilog code_vir2phy.v
analyze -f verilog cmem_if.v
elaborate cmem_if
current_design = cmem_if
/*uniquify because of the mig boundary cells */
uniquify
link
compile
a module with parameter such as:
module encrypt(
data_in, // data input
data_out, // data output
mpt // configuration data
);
parameter datalen = 24;
input [datalen-1:0] data_in;
input...
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