Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Xilinx_Modelsim

  1. X

    Simulation about 30MHz -> 1Hz clock divider

    Thanks for your reply. I just stimulated clock period in testbench. As your opinion, how can I get a 1Hz clock?
  2. X

    Simulation about 30MHz -> 1Hz clock divider

    Hi, KlausST Because I calculated clock cycle like this : 0.0333us * n = 0.5s So, I got counter number 15015015. Is it a problem with simulation?
  3. X

    Simulation about 30MHz -> 1Hz clock divider

    Thanks for your reply. I even tried to simulate my VHDL code and testbench, but I couldn`t get a accurate 50% duty cycle of 1Hz. How can I do?
  4. X

    Simulation about 30MHz -> 1Hz clock divider

    library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Clock_Divider is port ( clk,reset: in std_logic; clk_out: out std_logic); end Clock_Divider; architecture bhv of Clock_Divider is signal count: integer:=0; signal tmp : std_logic := '0'; begin process(clk) begin if(clk'event and...
  5. X

    Simulation about 30MHz -> 1Hz clock divider

    Hi everyone, I have a question about simulation (30MHz -> 1Hz clock divider). I used a VHDL code and Modelsim Tool for clock divider. Then, I want to get a simulation result about 50% duty cycle of 1Hz clock. I got a result for my simulation about 0.499s rising clock and 0.98 falling clock...
See more

Part and Inventory Search

Back
Top