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I want to design a current mirror which I1 copys I0, the voltage V0 across I0 must as low as possible such as one Vds voltage, but using the traditional current mirror V0 at least needs one Vgs voltage. The voltage V1 across I1 is not a big deal. How can I realize the mirror? Thanks a lot.
I found some words in the model file, it says:
$ 2. Bias
$ VDS <= |5|V, VGS <= |5|V, VBS <= |3|V
So I am not sure if I can use use VBS>3V in my design, then I ask foundary and it answer is :
It should judged by bias conditions, for example NMOS
If we add Vgs=5V, then the...
Is the parasitic diode's breakdown voltage higher than mos breakdown voltage(punch through?), right? In the manual the Vds breakdown voltage is about 8V, so if my assumption is true, the parasitic diode's breakdown votlage must be higher than 8V.
Then, If the parasitic diode doesn't breakdown...
Now I use 5V process to design HV 7.5V, the only problem is that I am not sure if the parasitic diode's (P+ to Nwell, Nwell to Psub, N+ to Pwell) revise voltage can suffer 7.5V in operation and is there any problem? The attachment is the Electircal parameter about this process, but I don't find...
Re: Can anyone introduce paper about designing analog switch
The consumption is only 500nA, and multiplexer is different from sample switch in ADC, the leakage will destroy the boostrapped structure.
The Cgb and Cdb is defined by layout diffusion size which is AD, PD, AS, PS. But I am confused that when I simulate using level 49 model the Cgb and Cdb exist without writing AD, PD, AS, PS parameter. I wonder how to defind these parameters in hspice program if I don't write them. Thanks!
I want 4kHz LPF, I design R=780K, C=10pF, and 3 same RC in series, the -3dB is about 4KHz, is the design right?
if right but the size is too big to integrate in IC, can anyone give me some instruction to design a low cost LPF, thanks!
I just want 4kHz LPF, I design R=780K, C=10pF, and 3 same RC in series, the -3dB is about 4KHz, is the design right?
if right but the size is too big to integrate in IC, can anyone give me some instruction, thanks!
I write res model myself as below:
.lib r_typ
.model hrpoly r scale=1 tc1=-2.1389e-3 tc2=8.7053e-6 vc0=1.0761e3 vc1=-1.9408e-4 vc2=-1.6639e-4 *hrpoly sheet resistances=1000
.endl r_typ
the temp coeffcient works, but voltage coeffcient doesn't work, is " vc0=1.0761e3 vc1=-1.9408e-4...
Now I use high voltage process, Vds can reaches 30V, Vgs can't exceed 5V, then my previous method using high voltage bandgap, OP, and power mos to generates inner votlage 5V is impossible, can anyone give me some instruction or suggestion of generating inner voltage 5V, thanks!
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