Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
If your clk is 100M (10ns), based on tsmc or umc foundry, on 5% timing margin is available for your design(slow case). For tsmc/umc/ibm/charted foundry, their timing models are accurate based on their process. So 5% marging is enough.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.