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The lockup latch should be inserted no matter how low the frequency is to make sure there is no hold violations between async registers in the scan chain.
DC run failed and reported:
Parent process select() error: EBADF (file descriptor invalid)
Error: dcfarm unable to communicate with process
Did anyone see this issue before and could help me?
Thanks!
Re: doubt related to STA
setup:
PrimeTime assumes that the corresponding launch edge is the nearest source clock edge occurring before the capture edge
hold:
The data launched by the setup launch edge must not be captured by the previous capture edge.
The data launched by the next launch...
DC will add "//synopsys isolation_upf ..." when inserting an isolation cell into the netlist, but I see some isolation cells are added without that pragmas, what case would cause this happen?
Have you anyone seen this case?
Thanks in advance.
-late
1. setup: (data path) x 1.05
2. hold: (clock path) x 1.05
-early
1. setup: (clock path) x 0.95
2. hold: (data path) x 0.95
CRPR will be set to true usually but depends on you.
BTW, the delay value in the picture seems not reasonable, tcq is too large.
1. clock gating is used for power saving.
2. you may add clock gating cells in the logics that in some cases they are not expected to be toggled so that the powe will be lower.
3. you can add standard clock gating cells mannully, or the clock gating cells may be inserted by tool automatically...
Some strange name appear such as "wire \a" in the dc netlist though "change_name -rule verilog" is applied.
How can I waive these unexpected names in the netlist and are there any other settings to suppress it?
Thanks!
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