Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
IM3 simualtion
hi all ,
I 'm looking the way to simulate IM3 current output vs input of full differential Opamp in cadence .could you pls suggest me how to simulate in cadence software .
Thank you so much
Miller Compensation
I got problem with my opamp design would like to seeking your help .
I am design two stage op amps using Miller compensation .
My design is shown in attachment . I consist of 2 stages in which the second stage is AB class op amp . I target my design for high bandwitdh opamp...
Dear all
I have a question which wanna ask all of you for help
I have transfer function combine s-z function like :
T=[(0.05s^2+0.56)/s]*[(0.73z+1)/z)]
do you know any code can plot frequency resonse of T by Matlab ?
Thank you very much
I 'm a final year student . I hope all of you can help me my problem when i simulate continuous delta sigma modulator.
question 1 : How i can model half delay block by Simulink ?
I try to model block ( z^-1/2) ( see figure attached ) but in Simulink library don't have block (z^-1/2)...
Hi can anyone guide me how to measure input refering noise by cadence ?
My step is :
- Noise -> Noise source -> Select node
then -
- simulation -> got to Result Browser -> frequency sweep -> innosise
In calculator i don know how to give out input refering noise...
Anyone can help me ...
I'm designning output buffer for LA with require output load =50 ohm
But after i design i dont know how to simulate to examine the value of output load by Cadence .Hope anyone can help me how to solve this problem .
Best regards,
hi , I got problem want ask all of you
I 'm design a limiting amplifier that need 4 stages which is cascaded ,each stage is
a differential pair .
When i design each each stage to satisfy its gain and bandwidth i must choose common mode input
also .But when all of stages are cascade ,the output...
i have a project which need the guide from all of you :
I 'm designing a LA amplifier but i'm not sure which one i should choose to satisfy
my requirement coz i 'm a newbie in analog design
This is a spec:
LA spec:
VDD:1.8V
Gain: 60dB (maximum), preferly gain adjustable by bypassing the...
I 'm desingning a two stages op amp .but i have one spec which i dun know to examine
offset<10mv
i dun know how to use simulation o cadence to see how much offset of my op amp ?
could any one tell me the method for check this spec?thanks
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.