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Hello, all,
I have a question about initilaizing the chip for test. Normally, we should modify the SPF file's MacroDefs.
The background is:
1. RSTn signal is scan test reset
2. XXTI signal is a normal signal (not DFT signal)
3. Before test chip, the following operation should...
Yes, you're right. At present I used I multiplexors to solve this problem.
But as you said, if I insert posedge clock_gating cell after an inverter, during scan test, all test clock should be in off-state, but after an inverter, this clock is in active-state. And this state can not initialize...
Hello, all guys,
In my library, I only have posedge clock_gating_cell, so for negedge flip-flop, I can't insert clock gating cell as my wish.
After synthesis, I found because of no negedge clock_gating_cell, PowerCompiler creates them by latch and logic gates, but when I do scan...
Use multi-vt library, good power managerment scheme, and use floating prevent circuit between 2 different power domains, also power gating cell for power domain
I need some training material about Magma CTS or Astro CTS
I am learning CTS now, I hope somebody can post some training material about this.
Thanks a million !
Hi, all,
Now, I encounter a very strange problem when I stitch the sub-block scan chain noto the top level.
In the past, I usually used this hierachical scan method to insert scan.
But this time, when stitch the sub-block scan chain (about 15 scan chain, 180 cells per chain) onto...
Hello, every one,
I have a problem.
When I connect the sub-block scan chain on top design. On the wrapper of this sub-block will be generated net test_si ports, the test_si ports I created earlier on wrapper are not used and tied 1'b0.
Please see the picture.
why put lockup latch at the end
Thanks, John.
1. In my design, there is no negedge flip-flop, only posedge flip-fllop. However, some logic can be around posedge flip-flop, such as inverter. So an inverter and a posedge flip-flop equal to a negedge flip-flop. In this case, no negedge flip-flop...
lockup cell
Thanks, John.
You are right. But my test clock can be controlled on top level. They are external clocks. Do you think it is possible to control the timing for a big SoC design ?
About lockup cell:
Now, in my design, every scan chain has only one test clock. So I found no lockup...
lock up latch
Hi, everyone,
We know, DFT Compiler inserts lockup latch between adjacent scan FFs if they are triggered by different clocks and the test clock waveforms are the same.
Use the command set_scan_configuration –add_lockup ture
However, in this case, how can we set false path when...
Following is my understanding, I hope somebody can help me for understanding.
There are two kinds of atpg test: low speed test and at-speed test.
When at-speed test, I found we didn't need to change the frequence of test clocks.
The difference between low speed and at-speed is in its SPF file...
Re: [HELP] Generate test coverage for sub-module after top-s
Thank you, John
I use Synopsys DFT Compiler, I hope there is hierarchical coverage command but I can't find. I hope somebody can give me some hints.
In my drc check report, I found many clock violations about Clock PIs off did not...
clock pis off did not force off clock
Hello, everyone,
I have finished the top scan insertion, but the test coverage is just 90%. Now I am analysing the reason.
I want to get the test coverage of each sub-module in DFT Compiler after top scan.
However, I don't want to set current_design for...
Hello everybody !
I am doing scan insertion under 65nm using DFT Compiler XG mode. When I finished the scan insertion, I checked the dft_drc report before and after scan.
In dft_drc_before_scan.rpt:
There is a warning TEST-121 said a clock_gating_cell can't be made scannable because it is...
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