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Thanks for your reply ....
After hours of survey, I'm not quite sure my current understanding is correct or not.
set_max_fanout VALUE DESIGN
- this would constrain all the net's fanout with stricter value e.g. min(VALUE, lib or DC's default settings)
set_max_fanout VALUE [get_ports...
In my case, I would make the input as multi_bit, and divide them in the always block inside module.
module top(
input [4:0] in_data,
input clk,
input rst_n,
output valid
)
reg b[4:0];
integer idx;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
for(idx=0...
I've been doing a lot of survey article for fanout for design compiler.
But for some technology process such as 90nm/.18um , our target library (.db / .lib) has already the settings of max_fanout/ max_capcitance for our design, but in 4x nm process, I can't find the max_fanout in .lib file
1. Is...
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