Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by william_qiu

  1. W

    Problem with inserting scan and DFFs

    Re: insert scan problem use command remove_attribute xxx dont_touch
  2. W

    DFT compiler question

    dft pad hi bendrift Could you give a detail description of flow? Or could you post your script? Thank a lot!
  3. W

    DFT compiler question

    dft io pad When I use DFT compiler to insert_scan i find if i insert_scan at chip level, I have to write a "gate level" pad model. For DFT compiler can't deal with pad correctly. The pad model i wrote contains only some AND BUF gates. But i found still sometimes DFT compiler can't understand it...
  4. W

    Help: asynchronous FIFO design!

    how to design a fifo there's a paper about asyn fifo design https://www.sunburst-design.com
  5. W

    What is synthesis xc_props = "INIT= " ??

    synthesis xc_props INIT attribute is used to generate LUT equation here's a example from xilinx Test case for using INIT attribute: -- 4 input comparator with chip select example. -- Given the signal DATA_IN (3 downto 0), the LUT equation is as follows: ~DATA_IN(3) * ~DATA_IN(2) *...
  6. W

    Important question on verification

    Lots of things should be considered. The most important thing to be remebered is for FPGA you may change your design as will but for ASIC the chance will be rare.
  7. W

    I used asynchronous reset in my design, and now found...

    Do you mean the re-sync circuit can't be covered by DFT?

Part and Inventory Search