Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
dft io pad
When I use DFT compiler to insert_scan i find if i insert_scan at chip level, I have to write a "gate level" pad model. For DFT compiler can't deal with pad correctly. The pad model i wrote contains only some AND BUF gates. But i found still sometimes DFT compiler can't understand it...
synthesis xc_props
INIT attribute is used to generate LUT equation
here's a example from xilinx
Test case for using INIT attribute:
-- 4 input comparator with chip select example.
-- Given the signal DATA_IN (3 downto 0), the LUT equation is as follows:
~DATA_IN(3) * ~DATA_IN(2) *...
Lots of things should be considered. The most important thing to be remebered is for FPGA you may change your design as will but for ASIC the chance will be rare.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
