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Recent content by Wiljan

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    Please can you explain me this font 8X8 row and col adress

    You will need to tell the FONT look-up ROM what character to show eg A,B,C....(ASCII) and what Row (Line) and Column(Pixel) To make it a bit more easy to use you will typical write your text to a RAM with the message to show like (Hello World) So you will also need to tell the RAM what output...
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    Please can you explain me this font 8X8 row and col adress

    Re: please can you explain me this font 8X8 row and col adress You are not mention the surrounding circuit so it's a bit hard do know what you want to obtain, but try to have a look here this is a good explanation of how a font are used for VGA https://www.fpga4fun.com/GraphicLCDpanel4.html
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    Quartus / Prime floor planning / atoms to obtain best fMax

    I will try to see if I add even more registers between the M10K stages Also I will try to press the constrain a bit more. And see if I can do some TCL script to make floor-planing a bit automatic. Thank you for feedback.
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    Quartus / Prime floor planning / atoms to obtain best fMax

    Thank you for giving inspiration Is for a proof on concept on an algorithm I do send in/out data over RS232 @115Kbaud I also have an RGB HV out to drive an LCD screen with some data all this I/O are driven by clk_25 Then I have all the internal algorithm running with clk_200 all pipelined I...
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    Quartus / Prime floor planning / atoms to obtain best fMax

    Hi When using Quartus or Prime for a FPGA project and you compile "place and route" will place the different logic as it find "best" somehow, a bit depending on which setting has been set in settings, this will get a fair fMax and does work for many applications. I do work on some project...
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    FPGA development Kit

    When you say "desktop Ram socket" does that mean you want the FPGA on a ram style PCB which fit int a RAM socket? (like a SOM) Something like **broken link removed** or a "stamp" which fits into PLCC socket https://www2.hdl.co.jp/en/press-release-list-2017/17g0058.html I have been looking to...
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    Altera Stratix 10 Hyper-Registers

    When you have a lot of BRAM and ALM you need more registers to load more cores into the FPGA when you get a lot of registers which gives hopefull more fmax and make you have more cores dues to loads of registers, then you need more ALM and BRAM to add even more cores. Kind of a chicken / egg...
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    Altera Stratix 10 Hyper-Registers

    Sure but I will then run out of registers since I need as many pipeline core's as possible and saw the Hyper-Registers as extra resources. There will always be a bottleneck :bang:
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    Altera Stratix 10 Hyper-Registers

    Interesting so did you had any look into the Hyper-Registers and any experience in the benefit of this? Reason for asking are I do work on a project where we need to have a lot of 8 bit in 8 bit out (256 bytes) s-boxes lookup stages in a pipeline core, and since the BlockRAM (ROM) M10K or M20K...
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    Generate desired random number in range in verilog

    Xilinx have one as well, it's old and there might be a newer around https://www.xilinx.com/support/documentation/application_notes/xapp052.pdf
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    Generate desired random number in range in verilog

    Re: range of lfsr depend upon input value LFSR are not real random you just the numbers will repeat in the same pattern over and over, but they are very useful for kind of random. Also they are build of a numbers of registers, for 8 bit you have 255 combinations (0 are not used since it will...
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    Altera Stratix 10 Hyper-Registers

    In the Altera Stratix 10 they do have Hyper-Registers in the routing layer / cross-point, it seems to be a very clever way to "pipeline" much more and thereby squeeze the fmax up like x2. I could for sure use that :lol: Are this "Hyper-Registers" technology available in any other FPGA series /...
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    image rotation with LUTs

    Hi Rotating of a non 90 deg like +-15deg are not easy even 90 deg can be difficult you will need SRAM You for sure want to read this PDF :-) https://www8.cs.umu.se/education/examina/Rapporter/robertn.pdf
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    VHDL 2x16 LCD module

    FPGA to LCD example have a look here https://www.fpga4fun.com/TextLCDmodule.html
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    please help for ic 74381 in vhdl

    The 74381 datasheet says; Carry propagate and generate outputs are provided for use with the ’F182 carry lookahead generator for high-speed expansion to longer word lengths. For ripple expansion, refer to the ’F382 ALU data sheet. Basic if you have a longnumber to calculate and use ripple carry...
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