Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The chip is a HDMI/DVI transmitter , one 3.3v power supply power down current should be less than 1uA, most cases it is 0.1uA , but some times the power down current shaking between 1uA and 550uA while I connect the chip with a DVI panel using a HDMI cable ,while separate the chip with the panel...
Thanks for your reply ! The VCO range can cover the pll output range, the pll should locked to 2.2V according to the separete vco simulation results,but the pll locked to 1.85V,in this case I check the reference input and the feedback signal,the two pulse phase are different ,but the vco control...
I use .tran analysis to run a pll ,the loop locked in TT and FF corner,but it locked to a wrong frequency(may be not lock indeed,but the LPF voltage looks like the loop have locked ) in SS corner,I have resimulated sereral times,but the results are alway the same ,who can give me some...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
