Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by well

  1. W

    use nc-verilog Simulation altera IP report erro

    I used NC-Verilog5.1 to simulate ALTERA's IP(the DDR2 controller ,use quartus9.0 to generate) , but encouter erro : ncvlog: *E,UMGENE (altera_mf.v,23972|5): An 'endgenerate' is expected [12.1.3(IE EE 2001)]. I find this erro from the file of altear_mf.v,the file used generate. like below...
  2. W

    how to find a good sdram model for simulation

    I have finded at Hynix Semiconductor too There is no model
  3. W

    how to find a good sdram model for simulation

    I have used SDRAM HY57V561620CTP-H in my system. I want to find SDRAM model for simulation. but I just find hyb18t1g160af_120(DDR2 SDRAM) model at Free Model Foundry. where can i find HY57V561620CTP-H model ? ths!
  4. W

    about spi slaver synthesizable module

    thanks for your reply! I found some problem about use external clock, if external clock have Jitter, maybe recieve wrong data. how can i choose a optimum method!
  5. W

    about spi slaver synthesizable module

    when spi slaver recieve data,use internal system clock better or external spi clk better? any document to refer? thanks!
  6. W

    how can I design SPI slaver by verilog

    I want to write spi slaver module which can be synthesized, but the asynchronous clock domain, I have write a spi slaver module already, but spi clock can't be fast or slow, the module can be use, but is not perfecte! somebody can help me ! thanks!
  7. W

    how to design pata virtual device !

    I want to devide command and data through this module, and the data can be encrypt by AES module, and the command can be transfer to Hard disk directly! but I don't know how to devide command and data! Anybody can help me?? 3X!!!!
  8. W

    how to design pata slaver?

    pata slaver just like virtual HDD,it can communication with PC
  9. W

    how to design pata slaver?

    I draw a diagram of pata slaver,you can know what I mean from it. thanks for all!
  10. W

    how to design pata slaver?

    hi! Anybody can give me some surggest about design pata slaver? where is beginning about the this subject? thanks!
  11. W

    use pwm to make speech synthesize

    pwm: 8 khz I can hear the voice clearly. there is no high frequency noise. I just change the clock of counter. but I don't why? thanks to all !
  12. W

    use pwm to make speech synthesize

    outputting speech through pwm thanks to all! let me feel not alone! please attention my post continue!
  13. W

    use pwm to make speech synthesize

    use a pwm to drive headphones thanks! I will do experiment according to your suggestion! I drawing my Waveform in the attachment. figure 1: pwm waveform figure 2: waveform when I connect speaker or earphone I can hear voice clearly when I connect earphone and some high frequence noise in there...
  14. W

    use pwm to make speech synthesize

    how pwm speech thanks for your reply! the sampling rate is 8khz,and the precise is 8bit. I don't have spectrum analyzer ,just have digital oscillograph. I measure the output of pwm when I connect the speaker, there is a high pulse.
  15. W

    use pwm to make speech synthesize

    pwm voice I have some question about my pwm speech synthesize module. I write a pwm module use verilog to make speech synthesize, I test this module on FPGA, I can hear the voice that i want to play. but there is some high frequence noice in the speech. can anybody give me some suggestion? I...
See more

Part and Inventory Search

Back
Top