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library ieee;
use ieee.std_logic_1164.all;
entity sort is
port(in0,in1,in2,in3,in4:in integer:=0;
out0,out1,out2,out3,out4:out integer:=0);
end sort;
architecture asort of sort is
type name is array(0 to 4) of integer;
signal x:name;
begin
x(0)<=in0;
x(1)<=in1;
x(2)<=in2;
x(3)<=in3;
x(4)<=in4...
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