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Recent content by wein

  1. W

    Sample code for ADI 21xx

    adi 21xx very good ! thanks
  2. W

    How to decide the set_load and set_driving_cell in DC script

    Re: dc constraints set load on your desig output port set driving cell in your design input port
  3. W

    HOT N-WELL Dummy layer

    Dummy layer is not tape out layer exp text layer.
  4. W

    Problem with I2C serial interface for EEPROM

    Re: I2C interface for EEPROM you can try added start & stop condition before you send data to EEPROM.
  5. W

    tools for digital ic design in window env

    simulation : Modelsim or ncverilog or VCS Waveform : nwave Debug : Debussy Synthesis : Design compile DFT : syntest or DFT compile APR : Astro LVS : Dracula
  6. W

    Code Coverage with HDLSCore

    You can use modelsim try it.
  7. W

    What's the difference between DFT and BIST?

    Re: DFT and BIST DFT is design for test BIST is Built in self test DFT is test by scan chain BIST is built in pattern generator
  8. W

    Assign statement in gate-level netlist (synthesized by DC)

    Re: gate-level netlist naming rule can solvent add naming rule -equal_ports_nets \ -inout_ports_equal_nets \
  9. W

    How can i make one standard cell delay zero in my design

    How can i only one standar cell in my design, when i read sdf ?
  10. W

    Is there a ATPG tool for Windows?

    Re: ATPG tool for windows mentor and synopsys and synyest has atpg tools.
  11. W

    How to design Sigma Delta ADC?

    delta sigma analog to digital converter vhdl who can give me sigma delta D/A converter
  12. W

    What is Link Library In Synopsys Design Compiler..?

    synopsys library compiler index search path are library & working dir
  13. W

    How to create HSPICE netlist???

    you can use synopsys nanosim simulatiom your design base on spice.
  14. W

    Pipeline a circuit with loop

    because your coding style is latch base design , you can change to assign data_tmp = { large combinational logic }; always@(posedge clk) begin if(reset) data <= 0; else data <= data_tmp; end
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