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Recent content by wee_liang

  1. W

    about SC OTA input common range?

    Why bother to set the CMRR specs when you haven't figured out it's impact in the modulator? Might as well just design the OTA first, then determine the CMRR.
  2. W

    How to build an IO pad cell design?

    Re: IO pad design Check out this book for a start. https://www.amazon.com/exec/obidos/tg/detail/-/0471253596/002-0518786-4403208?v=glance [/code]
  3. W

    Documents about variable gain amplifier at RF frequency

    Re: Variable gain amplifier Yes. But you can post your queries on the forum, you'll be surprise at the number of people who have done it ( I think).
  4. W

    Does AGC REALLY Necessary in GPS Front-end?

    gps agc Any idea what is the specs for the jamming signal?
  5. W

    [SOLVED] how to design a switch capacitor filter

    About the EDA tool, there used to be a Cadence add-on called SWITCAP a few years ago. I haven't gotten to see this add-on any more in the new Cadence version. Perhaps you can check on Cadence website whether this tool is still supported.
  6. W

    The advantages/disadvantages of VGA gain distribution

    VGA gain distribution I have a 3-stage VGA gain, ranging from large to small gain. What are the advantages / disadvantages if I distribute the gain from small to large or from large to small?
  7. W

    Documents about variable gain amplifier at RF frequency

    Re: Variable gain amplifier It was pretty difficult to get any books talking about VGA (I wonder why), but I eventually found something to read about in the Paul Horowitz (Art of Electronics .. sorry I can't remember the title well).
  8. W

    Comparison of two stage opamp and folded cascode opamp.

    two stage folded cascode two stage opamp - requires internal compensation folded-cascode opamp - require more voltage biasing - requires more vdd headroom - noisier + compensation through external load C That's what I recall from the top of my head ..
  9. W

    question about metal filling

    Thanks to others for clarifying my comments previously. My recommendation is as such: If metal dummies are huge (e.g. 100um x 100um or more), it's recommended to tie it to ground potential. If metal dummies are smaller, it should be OK to keep them floating.
  10. W

    How to get rid of DC offset from VGA output?

    VGA dc offset problem If DC offset is a problem in my VGA output, how should I get rid of it? (Calibration methods avoided please). Does putting ac coupling caps help? How do I bias the next stage? What value of caps should I use if I have a 4MHz signal?
  11. W

    question about metal filling

    Hi, Just for sharing. In my experience, there have been reports of damages on IC for large floating metal dummies. Most of them caused by discharging of static charges on these metals during CMP process. Through microscope, it was seen clearly a big "bomb" (i.e. burnt marks) was shown on...
  12. W

    Question about laying a 40Kohm resistor in IC design

    Re: Resistor Problem ! Yes, you can. 40kohm resistor is a reasonable size. But your sheet resistivity seems abit low for this particular process you're using. Are you using a digital process? Consider using nwell resistor if accuracy is not a major concern. Basically, ohms/square means the...
  13. W

    high impedance input in operational amplifiers

    Simple: To obtain maximum "voltage" transfer from one stage to another. Imagine you have a battery with a high series resistance (i.e. high input impedance) and hook a light bulb with it. You'll realise that it's dimmer than w/o it. That's because there is a voltage drop across the series...
  14. W

    Which opamp on 1.8 V supply in 0.15 has higher gain?

    Re: Opamp for 1.8 V supply 2nd option is better. 1st option burns too much current (remember you still need to create bias voltages for the cascodes). In fact, I'd suggest you to use a simple diff pair with active loads as the opamp for a start. You'd be surprise the bandgap performance may...
  15. W

    How to simulate inductor in hspice99.4

    It's hard to believe hspice not doing a good job in simulating fundamental elements (R L C). What kind of DAC topology did you use? While traversing through the binary values, did you allow the output to settle down before evaluating the values? Could it be that due to high current spikes...

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