Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I can use vcs-mx-2016 to simulate verilog or vhdl.
When I tyied to simulate vhdl and verilog in the same project, I was able to compile file with vhdlan and vlogan. However I got a error that event debug mode not supported, when I was excuting the generated file simv.
"Error-[SC_RUNNING_PCODE]...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
