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Recent content by watersky

  1. W

    three gm equations, how to use them

    all of three equations are right. the different is the choice : which parameter is fixed, which parameter is variable.
  2. W

    problem with duty cycle for given diagram

    produce 90KHz, a D trigger.
  3. W

    bandgap reference current accuracy and osc frequency

    how is the frequency of your osc calculated? for example: the frequency is changed with VCC. if the frequncy is fixed, a good bandgap voltage is normal, the current is calculated by vbg and R. the frequency is found this current and C. three variable parameter are vbg, R and C. vbg is good. R...
  4. W

    Decreasing noise in bandgap voltage reference

    Re: bandgap voltage reference first,must know where noise origin is from? if power or ground is origin, noise of the voltage reference is the same as noise of power or ground. these reference can be used in this ic. if noise origin is from other block, you can use RC filter or buffer
  5. W

    Low noise amplifier output impedance

    50 ohm is not compelling. capacitor and inductance are used for the aim that convert output impedance to 50 ohm.
  6. W

    Schottky Diode and mosfets

    if mos is used as half-bridge,they will work with inductor. when two mos of half bridge is off, the current continue flowing through the inductor from power or ground. this case need body diode of mos on. for the better work, schottky diode is used,parallel connect with body diode of mos.
  7. W

    about layout offset of fully differential opamp

    if your request is high, perhaps offset cancel should be used. In adc, not only opamp need use this technique, but also comparator does. In high precision adc, digital calibration should exist.
  8. W

    KT/C Noise canceling/reducing in analog or digital

    I know some adc designs use digital method to reduce noise. Some different arithmetic is used commonly.
  9. W

    Help me on Common mode voltage

    why can you not give 0.9V common voltage? write detail, we can understand your demand
  10. W

    The Layout of Power MOS

    different layout of power mos depend on your design and the posistion of power mos in the whole layout. The most important perhaps is several rings of power mos.
  11. W

    Help--about Ron of POWERMOS

    Simulate a resistor and power mos between vdd and gnd. Power mos need be post file from layout. Estimate Ron from data of foundry, and adding resistor of metal and via.
  12. W

    How to simulate fully differential ota with sc cmfb

    I simulate cmfb with stb analysis of spectre. Add iprobe of analogLib, which aim is connection when dc analysis, is not connection when ac analysis
  13. W

    problems in trans response of fully-differential OTA

    I guess the reason perhaps is your CMFB circut. Different CMFB circuit has different result.
  14. W

    about MIM capacitor problem

    I think if Cs has parasitic cap, Cf should have parasitic cap too. The parasitic cap of every C0 is the same. So (8C0+8Cpara)/(C0+Cpara)=8.
  15. W

    The difference between KSVR and PSRR parameters

    The KSVR vs. PSRR the below is from TI The supply rejection ratio, kSVR, is the same as the power supply rejection ratio, PSRR. It is defined as the absolute value of the ratio of the change in supply voltages to the resulting change in input offset voltage. Typically both supply voltages are...
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