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Thanks, but my problem is that I am a newbie to use FPGA and in particular this board. I want to have a simple design which takes a video input and displays in the on-board LCD. Though I have a knowledge of Verilog HDL, I am finding it bit difficult to get started with this board.
I found a...
Thanks for the reply ads-ee.
The VIP suite demo is based on the NEEK board which is bit different from Cyc III Emb Dev Kit. I am looking for examples/demos targeted for this board.
I am learning to implement simple image or video processing in Altera Cyclone III FPGA.
In particular, I have a new Altera Cylcone III Embedded Development Kit.
Can anyone please help me if there are any example image/video processing designs targeted for this board or any FPGA?
Thank you.
I am about to finish my Master's in Electrical Engg with Digital Communications specialization in Canada. I have good knowledge of DSP, MATLAB, FPGA Design using Verilog, Verification using System Verilog.
I have an experience of about six years (five years in Hardware testing and one year in...
Hi,
I am new to Verification and I learnt Verification using System Verilog.
I am interested in learning OVM/UVM methodology based verification.
Which is the best way to learn OVM/UVM? Should I attend any courses or can I learn by reading some manuals or text books?
Please help me...
Hi,
I am new to Digital Communications and MATLAB.
I am trying to implement the modulation scheme shown in the attached file <modulation_scheme.fig>.
My MATLAB code is here: <practice_comm.m> <low_pass.m>.
clc; clear all; close all;
%...
Hi,
(Sorry to post this here. I dont know where to post this.)
I want to know from which forum in EDAboard, I can able to download the e-books.
I am able to see the forum for the e-books request.
Can anybody help me?
Thanks.
Re: Why Engineers earn less salary compare to Sales n Market
The sales and marketting salaries are high because they are the people who will negotiate/convince the customers and get the projects for the company. If they are not there, and, they dont work hard, engineers will not be having any...
verilog timescale directive
Hi,
Why the directive `timescale should be used?
Suppose if we donot use the 'timescale directive, and mention the delays like #10, etc, how the simlator will consider it?
KSSR
blocking and non blocking in verilog
Hi,
Can anybody explain the concepts of Blocking and Non-blocking statements in Verilog? Or any good book/paper explaining these clearly..?
I just started learning Verilog and I am getting confused when to use these statements.
Thanks in advance.
KSSR
Hi,
I have done BE in E&C and worked for 3 yrs in the elctronics filed.
Is it good to do MS or MTech now?
Or continue with my job?
thanks in advance for the comments/suggestions...
Hi,
I want your valuable suggestion.
I am from India and I have been working for about 2.5 years on pcb functional testing, debugging, testings for standards like emc emi, etc....related to PCBs in Automotive domain.
I got a chance to work on FPGA design or ASIC verification now. I know...
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