Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by wanida

  1. W

    clock from library pll- need clock signal in the kHz in fpga

    clock from library pll If I need a clock signal in the kHz in fpga, is it better for me to use Megafunctions PLL and feed then divide the onboard clock signal with a factor as high as it can go or should I keep the division factor lower and feed it through a clock divider circuit (counters)? I...
  2. W

    quick help for novice - lcd code verilog

    initialize to zero verilog Hi. I'm learning myself. I have the same situation when doing counters. I use Modelsim and Quartus. I noticed that when in Modelsim, register values don't initialize to a value unless told. But in Quartus after programming, the hardware itself would initialize to a...
  3. W

    The best way to assign a fixed LOW to an input of a module?

    Re: fixed low inputs dcreddy, thanks. When I did Analysis and Elaboration, I got this warning that says the mentioned signal is connected to a 32 bit bus whereas my signal is a single bit, and the irrelevant bits are ignored. Is that a waste of connections or is it ok and considered better...
  4. W

    The best way to assign a fixed LOW to an input of a module?

    fixed low inputs Hello. Just need some confirmation. What is the best way to assign a fixed LOW to an input of a module? I want to instantiate a module into my design with inputs that I want to fix as LOW, do I need to declare a new internal wire signal and declare the width, and assign it to...
  5. W

    about wire and reg in instantiation

    Shahzad... you've summarized it well for me. Very helpful. Thanks.
  6. W

    about wire and reg in instantiation

    Yes, I declare the outputs as wire in the top module that instantiates the lower module. I find this out by trial and error. I am wondering if there is a clear guideline in any recommended document on this? Can I instantiate a module within an 'always @ (posedge clk)'? I tried but couldn't. So...
  7. W

    about wire and reg in instantiation

    Hi. I know that outputs that are in an always block must be declared as "reg" not "wire". Let's say module A has output outA and outB in an always block therefore they must be declared as "reg". e.g. module (inA, inB, outA, outB). My question: What if the module A is instantiated in another...
See more

Part and Inventory Search

Back
Top