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Recent content by walkon

  1. W

    Questions with Conditional compilation Commands in Verilog

    veilog conditional compilation Would you please explain more on that?
  2. W

    Questions with Conditional compilation Commands in Verilog

    verilog conditional compilation I have 3 sub-blocks and a top module load them with the conditioanl compilation command, here is parts of the top module. `define N45TT; `ifdef N45TT N45TT N0TT1 (.in(output1), .out(OUTTT1))...
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    How to make the FPGA board communicate with computer

    how to make fpga board Have an algorithm to implement: to use the FPGA board to process the Gaussian Noise generated in computer. How to read the generated noise into the FPGA board and how to load the output data from FPGA board and displayed on computer? Now I have no idea in my mind at...
  4. W

    Could real numbers in Verilog could be synthesized?

    If I want to write a Verilog module that include some computation with real numbers and fractional numbers such like 3.3*4.5 or 2.2/3.4 I know it will be okay with the simulation , but is it okay with the synthesis process? And, the input/output port of Verilog HDL didn't support 'real'...
  5. W

    Looking for tutorial on VHDL/Verilog simultation in Modelsim

    VHDL/Verilog simultation to sp, I think modelsim is easy to use. my experience with maxplus2 is so long ago that I forget all about it.
  6. W

    How to compute the square root of a real number in Verilog?

    verilog math functions btw: I don't know why Verilog don't intend to let its port support the real numbers input and output.
  7. W

    How to compute the square root of a real number in Verilog?

    square root verilog Thanks for you reply. I tried to use PLI. But it seems I could not even start to initialize the compile environment for PLI in Solaris..........
  8. W

    Sb. could show me some mixed VHDL and Verilog design code?

    Re: Sb. could show me some mixed VHDL and Verilog design cod Thanks for your reply, my modelsim version is 5.3 in Solaris when I try to vcom set.vhd, it says it couldn't load work.std_logic_util
  9. W

    How to compute the square root of a real number in Verilog?

    verilog square root Can anybody figure out how to compute the square root of a real number in Verilog? Are there some math library in Verilog as that of in VHDL? Thanks
  10. W

    Sb. could show me some mixed VHDL and Verilog design code?

    Sb. could show me some mixed VHDL and Verilog design code? moved here by davorin What the hell it has to do with "Analog circuit design" ??? (o; Please post in right section next time!
  11. W

    Which is the best tool for Top level simulations?

    Re: Top level simulations Hsim, definitely
  12. W

    What do you gain from Verilog2001 ?

    I think so , at least, it is possible for us to define the multi-dimension array and define an array of real numbers.
  13. W

    random pulse generator verilog

    verilog random seed How about generate random number with LSFR?
  14. W

    Could Verilog modules used together with VHDL modules?

    And, by looking back to the previous discussion, I get the idea that it could work. And the reason why I need to use VHDL is because I want to process some real numbers. And could the ports in Verilog be defined as the format of real arrays?
  15. W

    Could Verilog modules used together with VHDL modules?

    hi, Thanks for u reply very much. secondly, I just realized that I posted in the wrong board. I try to find my post on Analog Circuit Design just now. hehe I thought I posted there, but seems not. I am sorry for the inconvience I brought.
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