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Recent content by walker5678

  1. W

    Any ways to shorten simulation time

    I am using general averaged switch model, which is in the book " Fundamental of power electronics" , and write veriloga model to substitute the buck switch network, and do AC analysis, but found it is difficult to establish the DC operating point. I am still researching.
  2. W

    How to break circuit and add PAC source to get open loop gain plot in PAC analysis

    I want to plot the open loop gain dB20 and phase curve of a DC/DC converter using PAC analysis, but how to break the circuit and add PAC source? You cannot insert a L-C filter to isolate AC signal and pass DC signal, because the PSS analysis need to do transient analysis first, if you insert...
  3. W

    Doubt in guard ring details..

    If the PMOS or NMOS is used as ESD buffer, then you should make the source metal connection, which is connected to VDD or ground, as wide as possible.
  4. W

    Any ways to shorten simulation time

    If you are designing a DC/DC converter, you must have a clock frequency more than 1MHz, so the simulation time becomes very long. Is there any good ways to shorten the simulation time?
  5. W

    Doubt in guard ring details..

    What kind of guard ring do you mean? If it is only used to avoid latch up, i think there is no special rule for the width, because it is just a pick up function. If it is also used as the current path of ESD, it should be as wide as possible.
  6. W

    About analog IC system engineer

    I also think IC system engineer is a valuable job, just like the commander in a battle, he needs to analyze the situation of both enemy and our own and make decision. 孙子兵法里有句话“知己知彼,百战不殆”
  7. W

    Can I make such a circuit?

    I found a good structure, see this File:Cap-mult-op.svg - Wikipedia, the free encyclopedia
  8. W

    Can I make such a circuit?

    The theory is simple, but found it is difficult to realize, especially how to establish the DC operating point of the amplifier.
  9. W

    Can I make such a circuit?

    Can i use Miller effect to generate a very big effective capacitor, so that i can use it form a low pass filter with very low cut off frequency? See the attached pic. thanks.
  10. W

    what's the transfer function of this network?

    dedalus: yes, i also worked out this expression, but the problem is when design a compensation network, you should know the effect induced by R2 and C2, that is to say, estimate the position of p1 and p2. However, from the expression , we can hardly find the relationship between R1,R2, C1 C2 and...
  11. W

    what's the transfer function of this network?

    Please see attached picture, I know the expression of z1, but what is the expression of p1 and p2? I found it's complicated, any one know how to estimate the position of p1 and p2? Thanks. [/img]
  12. W

    stability simulation of bandgap

    Use stability analysis in cadence, break the feedback loop and insert iprobe cell into the loop.
  13. W

    ow to make my circuit work at corners SS, FF at 0 and 100deg

    corner simulation In IC610, there is specification based design environment combined with corner analysis tools, maybe it will help.
  14. W

    how to simulate leakage of CMOS switch

    Re: an interview question The left one can generate a very long trise or tfall by setting Vbp or Vbn to limit the current. For the right one, if Vbp is very high or Vbn is very low, it will act the same as the left one, however, if Vbp is low enough or Vbn is high enough , it can generate a...

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