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Have you tried get_pins -of_objects [your clock here] -filter [NAME =~ "b_comms.u_comms/u_pcie1/u_sync_pcie/*"]
This will return all pins from a specific clock domain in the given instance.
I'm not sure what you mean. Doesn't the function provided by SDK check for completion of the transfer? If you're trying to check if the data was correctly written to the destination, then you'll have to read it back and compare.
You'll achieve what you've asked in your post if you do what comment # 2 says, but you'll probably also need to implement some logic to check if the last slab of data has been received and then reset your lfsr_q register.
You will have data skew because 240 MHz is not a multiple of 100 MHz, so for some input samples you will have two output samples and for some you will have three output samples. If you want to upsample so as to have a continuous data stream for the filter, and also want to avoid data skew, then...
Like ads-ee said, you need to upsample your data. With your current design FIFO will always empty faster than it is filled. Why not get rid of the FIFO and just use flip-flops to synchronize data from 100 MHz to 240 MHz clock domain?
You could add an if-else condition on the assignment to "q" such that if read and write address are equal and write enable is also '1', then "q" should be assigned "data", else it should be assigned the value at read address from "ram_block".
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