Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by wadaye

  1. wadaye

    Pre-Silicon Validation

    Hi sriramsv, Normally we use both FPGA and simulation to do Pre-Silicon Validation. For FPGA the tools are Logic Analizer, FPGA board. For Simulation the tools are Simulators from any EDA Vendor.
  2. wadaye

    What's the most important in designing DDR SDRAM controller?

    Re: DDR controller Hi funster, If it is possible you can try Den@lis Ip FOR DDR, it has lesser risk than you design a new one.
  3. wadaye

    Advantages of using dc_shell in tcl_mode

    Re: dc_shell in tcl mode Hi barkha, With TCL mode you can find many useful scripts and many DC command only have TCL mode which you can't find ic dc_shell mode.
  4. wadaye

    Compile and Elaborate?

    Hi davyzhu, After you installed the tool, you will find a doc directory under the tool dir, at there you can find the tool manual. After you set the enviorment properly, you can use the command "cdsdoc" to view them, or you can go to the subdir direcly open it.
  5. wadaye

    What's the different bewteen VCD and SAIF

    Hi erich123, Briefly, SAIF is for power estimation. VCD is for debug, which has many information.
  6. wadaye

    Synthesis problem on Synplicity

    Hi OvErFlO, Yes. Most of the synthesize tool have this ability. You can add some directive in your RTL code to do this, please refer the synpl1fy reference manaual for more detail.
  7. wadaye

    How to do "DONT_TOUCH" in MAGMA

    Hi au_sun, Just hide them. Hiding a model prevents that single model from being used. Hiding an entity prevents all the models within the entity from being used. The command is: force hide entity | model Example: force hide $l/AND5 force hide $l/AND5/AND5X4
  8. wadaye

    how to learn ASIC Design properly?

    Hi nee_naresh04, If you wanna learn digital ASIC design, I think you'd better learn the digital logic first, then learn HDL language, then do a small design.
  9. wadaye

    What is a Frequency Doubler?

    clock frequency doubler Hi kumar_eee, Normally that is means a PLL, it's analog domain. You can find basic theory of PLL in many analog design book!
  10. wadaye

    the inout port in Verilog

    Hi wjxcom, You'd bettern instantiate the bidirection io in your rtl code, don't let tool implement it.
  11. wadaye

    Looking for documents about dual port FIFO

    Re: Dual port FIFO Hi kumar_eee, You can find the FIFO material on the Computer Orgnazation book. Such as Computer Organization and Design: David A. Patterson: ISBN 1558606041
  12. wadaye

    FPGA Tools can run on 64bit CPU platform?

    Hi dolby.yang, The mainstream FPGA synthesize tool such as Synpl1fy, FPGA P&R tool such as X1lin ISE, Alter@ Quartus can run on the 64bits CPU platform. You can find detail infomation in their release new or website.
  13. wadaye

    Explanation of the retiming process

    Re: Retiming And retiming will some combinational logic after the FF before FF, vice verse. You need more constranits when you do formal check if you retiming your design by tool.
  14. wadaye

    Set-up & Hold time Violation

    astro hold time For Setup: 1. pipeline the design. 2. OverCostraint when you synthesize. 3. Increase the synthesize effort. For Hold: 1. Insert buffer. 2. Increase the synthesize effort.
  15. wadaye

    What's the meaning of the switches access, rc, delay in NC Verilog simulator?

    Re: options of NCverilog Hi pavanP, I think the user manual in the install direcory can help you all the switch of NCver1log. And that is good than everyone else.

Part and Inventory Search