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Re: Where I can downlaod spice model of RF transistor of Phi
I'm finding on newer data sheets (like NS),
That they are including spice models now.
I think this is a good thing and I hope this
soon becomes a standard for all data sheets.
My advice is to go to Phillips site and look at
newer...
Usually active lows are prefered due to noise on lines.
What I mean is that usually there are noise spike riding on logic lines. If noise is on (for example 5v (high) line, it won't matter because it is riding on 5v.
The active low activates when line goes low (usually ground) so noise is...
visual spice simulator
When I took a PCB Design class, Our instructor gave us three projects to make.
1) We had to Breadboard every project.
- The projects had deliberate errors in their designs and could only be caught once we tested our projects on the Breadboard.
2) Then we designed our...
Re: about designing an ALU
If I read this post correctly, You might be experiencing overflow conditions.
Also ALU's usually do the add/shift method. So by the inherent design the answer
shifts also
a quick example
4 * 2 = 8
4 = 0100
2 = 0010
If the ALU does the shift/add the output would...
xst: 797
Compiler is complaining because you don't have a clock signal.
in your entity add a clock input
PORT(a, clk : in STD_LOGIC);
in your architecture try this
process (a, clk);
if (clk'EVENT and clk = '1') then
if (a = '1') then
counter:= counter +1;
this is one way to do it...
Re: Help with FPGA design!
@Mike;
What you described sounded like a J-K FF.
Look up the truth table and this will get you on your way.
Since you didn't say anything about a clock, The J-K might not help because it changes states during the clock.
Hope this helps
wa
ace-x wrote
I believe you have answered my question. The book I was using was Digital Design with CPLD Applications and VHDL by Dueck 2nd ed.
I was (at the time using my teachers copy 1st ed). Maybe I misread the chapter, but I remember reading about the clock event. It said you could use it...
pcb short circuit finding techniques
My experience follow what others have said.
But my usual rule of thumb is to troubleshoot this way.
1. A Good visual inspection.
- sometimes a strey wire strand or some other foreign object can cause short.
2. If no obvious defects are noted then I would...
If you are using VHDL, I think this can't be done.
I'm using the @ltera board but, my text book and the board confirms this too.
The problem is you are trying to use the same signal twice.
example:
process (clock)
if (clock'event and clock = '1') -- rising edge
then ...
end if;
end process...
Re: Do you know this Problem ? Answer to me cause and solut
If this were a standard video source to TV I'd say there was no problem but alignment of the vertical adjustment.
the top of standard signal is delibrately (usually first 3 lines) blank along with the lower part of the signal (the...
Re: What is the value of capacitance between a two layer PCB
Capacitence depends on the dielectric and plate size, for your problem your plate sizes will be the pcb's L x W - removed foil. dielectric is the material and space between both foils. Most basic circuit analysis books have the basic...
Could it be something simpler?
If reading by meter (unloaded) the meter is the load.
The meter has High resistance and impedance.
Now given this thought, when the load is connected,
the meter and load are in parallel. I think the truer reading is made due
to total load is less then resistance...
My first thought could be, that during initialization, the condition is not at a1.
if it at a2 for example, time is needed to complete sequence to get to a1.
since I see only 3 conditions, a1 - a3 and repeat..., the delay during initialization could be because you might have multiple...
If you are a student, you can go to @ltera's education development section. Just look for the UP-2 development board.
The UP-2 board contains a MAX-7000 and FLEX10K70.
The price is around $150 (US) for students.
Just check around for their board. If you use their search and type UP-2, you...
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