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Recent content by vrunda

  1. V

    Unsupported Switch or User Defined Primitive error in xilinx 12.4

    hi., i had done the schematic of a circuit in Dsch3 and generated the verilog code for the same using the option in "make a verilog file". This verilog code is then simulated in Xilinx 12.4. the code has no syntax error and was simulated successfully. but when i need to see the synthesis report...
  2. V

    how to ressolve the evaluation error that occurs while using cadence calculator?

    hello friends.. i am using the cadence calculator's "cross" function to measure the delay.. but i am unable to get the fruitful result because of the warning<calculator>evaluation error. can anyone help me out to come out of it.. can u suggest me how exactly to use it, which is the right way to...
  3. V

    how to measure delay of the circuit in cadence..

    Thank u very much.
  4. V

    how to measure delay of the circuit in cadence..

    thank u very much. when i have many inputs and single output can i follow the same procedure.. is that method gives correct value of the delay?
  5. V

    how to measure delay of the circuit in cadence..

    hi, i had done the 8bit priority encoding based comparator in cadence and performed the transient analysis. i need to measure the delay of the circuit. can anyone tell me the method or procedure to find the delay of the circuit in cadence spectre.. thanking u vru
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