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Recent content by voho

  1. V

    Interface Spartan2 -- Virtex6

    Dear I would like to connected I/O from spartan2 (@3.3v) to I/O in Virtex6 (@2.5v). Wich component do you porpuse in order to tanslate 20 bidirectionnal signals. thank s in advance regards
  2. V

    connect optical transceiver together

    hi it s possible to connect SFP Transceiver (λ=820 nm) with an other SFP Transceiver (λ=1310 nm). thank s
  3. V

    Rate SFP+ transceiver

    Dear, I would like to know if SFP transceivers that support 70Mbps. If so can you please suggest the part numbers. Thank's in advance Best regards
  4. V

    pipelined SRAM with FPGA

    Hi all, I would like to connect a pipelined SRAM to a virtex5 LX. It s possible? How to connect the adress input to fpga? I need a link to understand how it s work a pipelined SRAM Thanks in advance
  5. V

    MIG as DDR2 controller, virtex5

    Look if SysClk is connected in your virtex5 in pin I/O GlobalCLK
  6. V

    DDR2 controller, MIG for virtex5 design

    Before to use mig you need to choose witch memory do you want to use. For example DDR2 by micron and look at the data sheet about DQ an DQS. Dq is the data and DQs is strobe associed to this Data. more info at: https://www.xilinx.com/support/documentation/ip_documentation/ug086.pdf XAPP858 -...
  7. V

    Memory Interface Generator (MIG)

    Hi Device Family Support * Virtex-6 HXT * Virtex-6 LX * Virtex-6 LXT * Virtex-5 FXT * Virtex-5 LX * Virtex-5 LXT * Virtex-5 SXT * Virtex-5 TXT * Virtex-4 FX * Virtex-4 LX * Virtex-4 SX * Spartan-6 LX * Spartan-6 LXT * Spartan-3A *...
  8. V

    Interfacing DDR2 micron component to virtex5 Bank

    Excuse me but what is the link betwen USB protocol and routing DDR2? Thank s
  9. V

    Routing DDR2 automatic or manually

    Hi all, I use cadence and would know if it s possible to route DDR2 component to virtex5 automatically (spectra)??? Thank s in advance.
  10. V

    VIRTEX 5 QUESTION BANK LEVEL

    HI ALL you can have both single ended and differential inputs in SAME bank in Virtex5 thank s regards
  11. V

    Interfacing DDR2 micron component to virtex5 Bank

    hi all, I m looking for an operationnal schematic in order to connect a micron ddr2 to a virtex5 Bank IO. thanks in advance
  12. V

    How to change the time unit of the ISE software?

    Re: about ISim of ISE i think he depend on ISE version i m working with ISE11.1
  13. V

    How to change the time unit of the ISE software?

    Re: about ISim of ISE hi look at the top on the right you can choose ps,ns,us,ms, sec A+
  14. V

    how to design a clock multiplier in verilog

    you can use ip core in fpga look at DCM
  15. V

    ADC diff mode --> common mode

    Hi all, I use an adc ADS5440 with 13bits output LVDS (Do-D12& Do/ - D12/) pair connected in FPGA. It s is possible and what is happening if i use the output of this adc ADC ADS5440 in common mode (Do-D12) connected in FPGA. In UCF file i use only the pin Do-->D12 assigned during synthesis on...
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