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HI,
i am doing a project in ML402 and i want to display my output in hyperterminal .The synthesis is coming fine.I could download the program succesfully in the kit using impact. but not able to view the output. can any one tell me the procedure for viewing the output.
do i have to modify the...
hi,
if you are using fixed point multiplication multiply the fractional number with a constant say 100,represent it in a fixed point format(same as 3) and do the multiplication in same number format.
vny
Hi,
am sorry for the delay in reply .here are the details.
i am currently doing a project in verilog where i need to obtain pixels values from an image and use these values to calculate 2d dct. I am plannig to do in fpga .either virtex 4 or spartan 3.
so i need to load an image in fpga...
sorry for the delay and thanks alot for the replies . i actually made all the bits as 17 bits and did the calculations as i need minimum 16 bits to represent my final result .initially i checked the 13th bit and then adjusted the remianig bit as we used to do it in manual way . but in the long...
hello,
am doing my project in iverilog . i have reached a particular stage where i get a 17 bit out put from a 8 bit input(after multiplying and sign adjustments stages). now i want to revert back my 17 bit input to the first stage input register which is actually 8 bit. how can i round off 17...
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