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fastscan +tetramax
Fault grading has following steps.
Take EVCD from functional vectors
prepare them for tester by defining the events and strobes
Build model
then run DRC with nofile option
run vectirs in "good simulation mode' to validate simulation model and vectors as well.
then "fault...
Has anyone used both the tool for patterns generation to make apple to apple comparison and say which tool can give better results?
I am fastscan user all along and I would like to know if any anyone around here have any openions if tmax can handle any situations better than Fastscan?
like...
what is highz
One of the possibilty cud be that " the perticular pin is BIDI". By defning the input as high Z I.e. high impedence you are telling the ATE to not to drive tht perticular PIN.
This is what fastscan does when you constrain a BIDI pin as PO only using "ADD PIN CONSTRAINT"...
when you are testing TFT does this delay includes the propagation delay of the wire too? or it is just rising or falling time of the node to opposit value?
I would appreciate if any one can help me n this,
~V
dft interview question
Hi Badola,
Typical scan frequency is the frequency that most of the ATE's use when scaning in the data to the scan flops. it is typically around 1-10 Mhz.
Hope it helps,
~V
lock up latch in dft with inverted clock
Here are few interview questions from my previous interview.. These are more focused on ATPG generation and scan insertion.
How is logic transition fault is different from memory transition fault.
What are RAM sequential patterns?
Diff b/w Named...
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