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I have an SV interface definition. (Used both inside RTL as well as test bench top) (PS: this is only a tiny bit of the entire code)
interface bus_if(input clk, rst_n);
`include "bus_params.v"
logic [3:0] cfg_slave[0:1];
modport slave_port(input clk,rst_n,cfg_slave);
modport master_port(input...
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