Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Vlad.

  1. V

    Configuration Registers within an FPGA

    Dear all, Many thanks for your answers, I will use a generic signal register then. It seems to be the easiest and most efficient way. By the way, it will be a Xilinx 7-series FPGA. Cheers, Vlad
  2. V

    Configuration Registers within an FPGA

    Hi, Which is the best way to store/hold the state of the "settings/configuration" register within an FPGA that is part of a complex system? This is what I am thinking: Assuming a register frame of 100-bit length as follows, 012....XXXXXXX, where 012 are the first 3 bits that I use for...
  3. V

    Implementing a TCP/IP ethernet protocol within the KINTEX-7 GTX

    Hi, Many thanks for your answers. My custom KINTEX-7 board has a SFP cage and a RJ45 connection. Hence I think for now I will try the RJ45 connection to comunicate with a host. I am aware of the free cores from FPGA cores, and I can confirm that they work fine on a KINTEX-7, however, I have...
  4. V

    Implementing a TCP/IP ethernet protocol within the KINTEX-7 GTX

    Hi, I have a custom KINTEX-7 board that has one SFP port for ethernet communication. I would like to implement a TCP/IP ethernet at 1 G. Can someone point me to an example of a such design? I have been playing with various example, however I wasnt able to understand very much. Can this be done...
  5. V

    Data string length to be send out from FPGA

    Hi Barry, I am inclined to do that. However, my concern was about the length of the data which is to be set on PC to expect from the FPGA, hence a larger number or lower number of bytes without modifying the buffer settings in the PC GUI. But I think I will find a way to config the receiver in...
  6. V

    Data string length to be send out from FPGA

    Hi, I have custom FPGA board which has a lot of peripherals like: temperature sensors, RTC, ADC etc. The board has also a high speed mezzanine connector to communicate and take data from some high- speed ADCs and not only. Right now I am thinking to design the firmware in term of the length of...
  7. V

    AXI 4 Stream Data Width Converter

    Hi, Many thanks for your input. I manage to get it work by adding an counter based case structure and i keep ready always '1'. Now its working fine. Best, Vlad
  8. V

    Bluno link with RF-BM-S02 CC2540

    Hi there, I am designing a custom hardware which has an Atmega328P with RF-BM-S02 CC2540. Since with my smartphone/PC bluetooth I didnt manage to see them, I have now the Bluno link adapter which can be found here: https://www.dfrobot.com/product-1220.html . But, since I dont have any clue...
  9. V

    AXI 4 Stream Data Width Converter

    Hi, @TrickyDicky Not yet, But I am looking at the signals with an external logic analyser and I am trying to figure out where is the problem. @ MarkPh Thanks for your suggestion, I have implemented it but still not working properly. Data is set correctly in that register, but is changing...
  10. V

    AXI 4 Stream Data Width Converter

    Hi again, I am trying to process data by filling and 64-bit buffer with received data from an 8-bit AXI4 stream master. I started with the following approach, but till now seems to fail to work as I expected. ---AXI4 stream master--------------------------- signal rx_data ...
  11. V

    AXI 4 Stream Data Width Converter

    Hi, Thanks for your reply. Yes, I just need to be able to fill an 8 byte register with 1 byte data bus coming from AXI. And also to send 50 bytes to MII with 1 byte data bus. I will try to do it with pipeline, If I have some problems,I will post again. Thanks, vlad
  12. V

    AXI 4 Stream Data Width Converter

    Hi there, I need to convert (Upsizing and Downsizing) two AXi 4 Stream Slave and Master. Hence, I want to do the following: -from 1 byte AXI4 Stream Slave to 50 bytes width; -from 1 byte AXI4 Stream Master to 4 bytes width Please note that the 1 byte AXI4 Streams both slave and...
  13. V

    FPGA Ethernet interface

    Hi there, I am thinking to replace my UART core from my FPGA system with an Ethernet one. Right now I am using a commercial board to control my system, hence it has a PHY interface for Ethernet, NEXYS-4 DDR board. I am using VHDL and VIVADO for this. I want to place my system in to a intranet...
  14. V

    DAQ system with FPGA and 1KHz sampling rate

    In the past I had used sync chars in my applications with microcontroler, but I did not get any transfer error, like the one pointed by you, but yes of course you are right, there is a chance, and data will be screw up, so for that I added also the byte counting between As. Anyway, I am more...
  15. V

    DAQ system with FPGA and 1KHz sampling rate

    Yes, you are right with the calculations, I just put the number without the additional ones, you had included also the start and stop bits, which is also my configuration 10 bits for 8 effective bits (1 start and one 1 stop bit). Regarding the frame sync, I am aware of that, till now I had used...
See more

Part and Inventory Search

Back
Top