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Recent content by vivekanilvivek

  1. V

    cortex mo design start

    Hi, I am trying to build the peripheral around Cortex-M0 IP core thorugh AHB-lite system. Right now I have to integrate Cortex-M0 with the DDR2 SRAM (1Gb) through AHB lite. I find on internet which shows interfacing only through core generator (MIG). Is there a way I can use Xilinx core...
  2. V

    microphone for heart sound

    Thank you sir. That helped a lot
  3. V

    DDR2 memory interfacing

    Hi, I have been trying to interface DDR2 memory(external) (1Gb) to my FPGA. I have been using Atlys spatran 6 board which has external memory of 1Gb. On FPGA Cortex M0 processor is running. I have to interface this memory to Processor running on my board. Can anyone suggest who has worked...
  4. V

    microphone for heart sound

    Actually We have already made an arrangement for stethoscope and microphone. But the thing is Signal we are getting is quite noisy. we need to find exact location at which S1 and S2 sound is occurring and some signal processing on that. I just need some high sensitivity microphone(name or...
  5. V

    microphone for heart sound

    Can anyone suggest the appropiate microphone for capturing heart sound ??
  6. V

    cortex m0 design start IP core

    Hi, I am trying to build the peripheral around Cortex-M0 IP core thorugh AHB-lite system. Right now I have to integrate Cortex-M0 with the DDR2 SRAM (1Gb) through AHB lite. I find on internet which shows interfacing only through core generator (MIG). Is there a way I can use Xilinx core...
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