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Recent content by vivek_vlsi

  1. V

    i need verilog code to filter out ethernet MAC

    i need verilog code to filterout ethernet MAC how to filter MAC address only from Ethernet packet?
  2. V

    I need to generate variable frequency in verilog

    its sine wave only .using LUT i generated.values got from MATLAB. frequency i varied accoring to your solution.its simulation of reflected wave required.how the velocity and acceleration of the moving body affect the generated sine wave from it.We can input velocity and acceleration to sine wave...
  3. V

    I need to generate variable frequency in verilog

    Hi,It was all good with your help.Now I have to incorporate velocity,acceleration and Doppler shift to the sine wave generated.We need to assume this sine wave is generated from a moving object.Hope you got the idea.How can we vary the frequency and amplitude of the sine wave w.r.t these...
  4. V

    I need to generate variable frequency in verilog

    Hi,i used frq divider logic initially,but for my required range how many counters i need to use for pretty high resolution? Also we cant use parameterized counter if synthesizing right?
  5. V

    I need to generate variable frequency in verilog

    Thanks, My target device is Spartan 6.I think i can use dds core which is nco available. I went through the dds spec now.What i understood is we need to give Δθ ,the phase increment value to get a desired frequency.Can we vary the out put frequency dynamically by streaming phase increment...
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    I need to generate variable frequency in verilog

    I need to generate a variable frequency 1Kz to 1Mhz in runtime from a 200 Mhz clock . I need to use verilog and simulate in Modelsim.What are the possible ways?
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