Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Thanks for reply.
Resistor for common mode feedback are 10 Mohm, while there is drain to source potential of each and every transistor is 1.5 to 2 times that of VDS(saturation) and input is sinusoidal 100 mV (p-p) and differential in nature too.
Hi guys,
I am trying to design a folded cascode operational amplifier with pmos input and a dc gain ≧70 dB in UMC 180 nm. All the transistor are working in saturation, but, I am getting gain -61 dB.
Can anyone please suggest the problem with this and how I can correct it.
- - - Updated - - -
thanks for the reply FvM.
Thanks for the reply pancho_hideboo, but What is "pIIMMLib" which library is this??
Thanks for the reply asdf44,
Please see the image attached with this reply,
https://obrazki.elektroda.pl/9756054400_1486740617.png
This is a second order sigma-delta modulator (all...
Re: discrete time integrator with transfer function = 1/(1-Z^-1)
Thanks FvM for the reply,
First I apologize for typing gain = 1000.
1. But this is an ideal delay free integrator isn't it suppose to give gain = 1/sqrt(2) only.
2. when I am giving input 200 mV (peak-peak) then the output is in...
Hi,
I am designing a discrete time integrator with transfer function = 1/(1-Z^-1) using model writer of the cadence virtuoso, below is the verilogA code of the integrator. But I am getting a gain of more than 1000 in the output, when applying an input signal of 900 uV (p-p).
I added the...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
