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Hi,
Thanks for your quick reply!
Yeah, you are right! we can't use this command,
set_input_delay 1 -max -clock D_CLK [remove_from_collection [all_inputs] [get_ports CLK_A]]
But how to seperate inputs of specific clock from all_inputs???
As you mentioned we can specify the inputs...
Hello all,
Greetings! Hope you all doing good!
I have a quick question about synopsys DC synthesis.
I have a top module called "topblock.v". This module has two sub modules called "block1.v", "block2.v".
The outputs of "block1.v" goes to "block2.v" as the inputs but the module "block1.v" is...
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