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Recent content by visualart

  1. V

    Gated clock for power saving

    add the option gate-clock,when you run the design compile
  2. V

    How to force Precision_Synthesis to ...

    ungroup -all flaten so , all components are on the smae level
  3. V

    Cadence License server migraiton to Linux

    Can't I see you! U want to abnegate the SUN Server for your license, or U will use the RHEL for your EDA server? The sun was slow to run the EDA tool, BUT IT is competent enough to surpport the license service. BRs
  4. V

    The advantages of scan chain balancing in DFT

    Re: Scan chain balance balance? what do you mean? Has the scan chain the same number regsiters? If so, You may define the number. BRs
  5. V

    Anybody uses Hercules?

    For the 65nm process , you may use the assura too. The new version of assura is a excellent tool box!
  6. V

    When should DFT come into the flow?

    DFT Strategy you may insert the dft scan chain after the synthisis. do test synthesis, and generate the partterns for test. BRs
  7. V

    cadence soc encounter 8.1 installation movie

    your media doesnot match your installscape, or The media information is imcomplete, Yu may try to install manually. Good lucky
  8. V

    who can share a sample Design Complier synthesis script?

    The script must be matched the project! If ONLY learn, you may use the synopsys training material. Good lucky
  9. V

    What would happen IF I forgot to add the strap? SOS!

    the straps are used to reduce the IR drop! with 0.13um technology , hou much voltage will the 1400um length wire bring on ? I ......
  10. V

    What would happen IF I forgot to add the strap? SOS!

    what would happen that I forgot to add the power/ground strap in my project? the project area 2x2mm,core 1.4x1.4mm, o.13um technology, Because my carelessness, the last layout mistake the strap, NOW , the masks always were made. what would happen? Can the chip run? How to retrieval it...
  11. V

    Clock Uncertainity- max operating freq, max freq calculation

    Clock Uncertainity you may get the maxum frequency by the fellow express: max freq = 1/(16+0.2+0.5+T(clk to Q))
  12. V

    Clock Gating setup and hold time

    what is clock gating check You may margin the enough timig for the setup and hold, SO, the layout and STA can easy match the need of the library. GOOD LUCKY
  13. V

    how to generate fram view using Astro?

    fram view purpose you can get the tlu plus model with running the itf2tlu+ , or transfer it in the StartRCXT
  14. V

    How to insert your IO pads and POWER pads to your design ?

    astro pad netlist u can insert your pwoer pad with running the coomand : insertPad padname insertname .... In the astro, the power pad was called dirty power
  15. V

    Suggestions for a RISC core !

    RISC CORE u may find the aaARM, the nnARM is a RISC Core with compatible ARM7 BRs
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