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Well , the FPGA is operating at 160 MHz with 10 MHz clock input.
It is connected to 16 bit DAC.
DAC(AD9726) clock is given by FPGA clocked at 160 MHz.
LPF used is 50 MHz filter.
Expected output is a BPSK modulated tone with bandwidth 20 MHz.
For test case we used only carrier where we...
Dear all, I am new to this forum.
Here I have one question. We have designed a board which constitutes a FPGA clocked by 10 MHz, followed by a 3 DAC's which is followed by transformer, LPF and Amplifier.
What I am expecting is a 20 MHz pure tone at outputs of 3 amplifiers of 3 DAC's.
But...
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