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Recent content by vishwanth

  1. V

    H-tree Clock Synthesis using Design Compiler

    Hi I was wondering if anyone has ideas on how to synthesize a h-tree clock network using Synopsys Design Compiler.. I have some PTM models for 32nm NMOS and PMOS. I would like to use CMOS Inverter as a buffer at each branch/leaf. I would like to synthesize a 3 level h-tree to analyze the...
  2. V

    H-Tree Netlist for H-Spice

    Hi I'm a undergrad student doing research on H-tree I'm having a hard time writing a Hspice netlist for H-tree. I intend to use synopsys tools for timing and skew analysis. The driver/ buffers are 32nm CMOS's Any help with sample netlists, synthesis codes or any piece of advice. If you...
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