Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Vishu21_95

  1. V

    Factors deciding Silicon Wafer Thickness

    Hi, I want to know 'what are the factors which decide the thickness of silicon wafer which will be used as a substrate?' Thanks.
  2. V

    Difference between S3 and T3 Layer used in 22FDX Technology

    Hi, I want to know the difference between S3 and T3 layers used in 22FDX technology as both are mentioned to be deep n-type implant for isolation of pwell regions in DRM!! Thank you!
  3. V

    Why is pmos and nmos put vertically and not side by side(horizontally)in ic layouts?

    Yeah this can be the case!! More the advantage of keeping pmos and nmos vertically is that all the pmos can contained in a single well which will not be possible of you keep them side by side.
  4. V

    Why is pmos and nmos put vertically and not side by side(horizontally)in ic layouts?

    I have Worked on 22FDX and 28nm node Technology and there is no convention of placing nmos and pmos in a particular fashion you can either put pmos and nmos side by side or one down the other!! If we talk about channel: Well in planar IC you will never see a vertical channel ,the channel is...
  5. V

    [SOLVED] Use of hybrid layer in devices

    Are you saying that devices having SOI layer will not have hybrid layer and vice versa???
  6. V

    [SOLVED] Use of hybrid layer in devices

    Hi, I want to know the use of hybrid layer in devices!! In DRM it is mentioned as : Bulk exposed region,removed SOI Please explain!!
See more

Part and Inventory Search

Back
Top