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Recent content by vipin_vasudevan

  1. V

    drc error in cadence--hot nwell

    virtuoso hot nwell Hii, If the problem still exists then u do check the labells.whether its multilabeled or a soft connect with substrate markers. rgds Vipin
  2. V

    What is soft connection in layout?

    softconnection Hi , Soft connections are mainly the connections which is made thro diffussioons.Some times people may calll the same for label short ( x :)also. Rgds Vipin
  3. V

    What is the structure and working method of Dmos?

    Hi, I need to kno the layers used for making a Dmos ? what is LDPI ?and these region forms ?, NDWND ?and why its used for NDMOS? How is gate and bulk structure ?Plz give me ur replyss! RGDS Vipin
  4. V

    GDS Streaming from Viirtuso to Astro?

    I need to hav a suggestion to get back full floor plan info including Row and Cell Placements after streaming the gds to Astro . Since i lost the Astro Database . Now i hav only the virtuso Data and astro Refernce libraries ,techfile . Is there any way to dump floor plan from existing...
  5. V

    Virtuoso used to design pcb?

    export dxf virtuoso HI , As I know virtuso is intended to use mainly for IC design. For PCB u can go for Aligro ,BoardStation,PADS,Portal,ORCAD ETC.. The designing consepts are more simpler than IC Layout design . RGDS Vipin
  6. V

    Dummy transistor and decoupling capacitor

    Hi, Connectiing dummy mos as decoupling cap may be a little risky ,if it damages the sio2 layer.

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