Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
I have a basic doubt. In VHDL all process are concurrent, i agree, but what about the statements in all these processes. Are they sequential or concurrent or pipelined ?
I have a doubt in sampling theory, that too in aliasing ambiguity,
x(n) = sin(2*pi*(f + m/nts)*nts)
x(n) = sin(2*pi*(f + k*ts)*nts)
In the above equation, why m should be integer multiple of n. What if m is fractional multiple of n.
Hi I just want to known, once i have written a piece of HDL code what happens in synthesis and implementation. It is vendor dependent or the procedure is generic to all vendors.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
