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I will rather say 16 bit SAR ADC is doable provided the MSPS is not very high !
Go for Time Interleaved SAR ADCs !! 2 SAR ADCs 8 bit each working in time-interleaved fashion will do ur job !!
Added after 1 minutes:
If its Audio, its very possible !!
Guys making a SAR logic is very simple.
A shift register with asynchronous reset will do the work you.
Refer to Dual Time Interleaved ADC paper by Ginsburg & Chandrakashan. I can't recall the year.
Added after 5 minutes:
Refer to this paper:
Hi Guys,
I am looking for some numbers so as to get an idea of magnitude of top plate and bottom plate parasitic capacitance in MIMCAPs (data for other kind of capacitance implementation is also welcome ;-) ). Can this information be found in PDKs ?? Any paper on it is really welcome.
Second...
I am using Calibre for DRC, LVS & PEX in Cadence. DRC and LVS are running fine but i am facing a weird problem in PEX. After extracting the parasitics and making a symbol and simulating it by including calibre view, its saying No DC path from some node(usually VDD) to ground. BUt schematic is...
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