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Hi Badrino,
I have been in industry for little over 1 year and I have done SoC verification during this time which makes me a relatively a newcomer. So, I can tell you only what I have encountered. In verification (dynamic ) you have to check whether the design is working properly, so when the...
What does it mean when we say that in GATE Level the whole design (may be netlist) is flattened? I had done GATE Level simulation in 2 steps...firstly Zero Delay..and then Standard delay format (SDF). What is the advantage of using Zero delay? Also how in terms of timing does it differ from RTL...
Hi Dynamic verification is when you actually run a testcase and you can see in the waveform of different signals that they are changing their values during the running of the testcase..(they may take a constant value in some exceptional cases). Formal verification ...from what I have encountered...
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