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Recent content by Vigneshrajaece

  1. phase error

    phase error

  2. DLL initial lock

    DLL initial lock

  3. DLL

    DLL

    snapshots of delay locked loops
  4. V

    tested output of delay locked loop in cadence spectre tool in .18um technology.

    This is the phase detector , CP , VCDL output of my DLL..
  5. V

    tested output of delay locked loop in cadence spectre tool in .18um technology.

    Hi... i cant sort out what the problem is from the waveforms ... can u send me the schematics of the components of DLL so that i can sort out what the problem is... ?
  6. V

    tested output of delay locked loop in cadence spectre tool in .18um technology.

    Hi, I am also working on delay locked loops.. I too have the same problem ... my output is not locking with my input signal.. To measure power, in the ADE window select outputs -> save all... In the window appears0, enable the check box all in power in subcircuits .. Then run the...
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