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Hello,
I am designing circuit (using 0.18um). Usually, by biasing Vgs < Vthreshold of MOSFET, we can push MOS into sub-threshold region. My curious question is: How much value of Vgs is "good" as a "rule of thumb"?
I have referenced to "Trade-offs and optimization in Analog CMOS design" book...
Thank you. I check that libddbase_sh.so is not missed. I am supported by a local-designated supports center so I could not resolve this using Mentor customer support. I am still looking for a solution.
BRs,
Dear all,
I am facing one problem during Calibre PEX. The error appear as: "Calibre View generation encountered a fatal Error. Please consult the logfile for messages."
When I check the log file, it shows the content (as below). Do you have any idea or you met same issues?
Tks for your help...
Re: "Local feedback" concept in Opamp and OTA
Thanks CataM
I am wondering, why the op-amp need the negative feedback while the OTA not. Can we used OTA with negative feedback? If it is possible, what is the different between OTA and Opamp in that case? Furthermore, I have read that the OTA can...
"Local feedback" concept in Opamp and OTA
Dear all,
In compensation networks, we use OTA and Opamp as EA in DC-DC converters (also another applications). The different between them is the physical connection of the compensation network with respect to the inverting input of OTA or Opamp. In...
Dear all,
I wonders what is the difference between the connection of compensation networks using OTA as Error Amp for dc-dc converter (please take a look at the attached figures below). The first one connects back to negative terminal of OTA while the second one connects to gnd.
Appreciate...
Dear,
I know a little bit in dealing with Candence-CentOS (I manage the serve of my Lab). As Mr. Bigboss said, CentOS7 is not good for Cadence. The Centos6 is okay.
After installing the CentOS:
1. Update your license
2. You can change the .bshrc or .cshrc as you want (I used .cshrc). In order...
In this BGR circuit, You should determine where is the negative feedback loop, and then break the loop with iprobe. The position of breaking at the output of opamp is wrong, I think.
BRs
My sincere thanks to Mr. Dick and Mr. KlauseST,
For clarification, I am doing "digital LDO). The reason I posted this thread is I want to focus on the worse case of VDD with fluctuation mainly caused by load transient condition that the "load" does still properly function. The LDO here is pure...
Recently, my research focuses on design power supply (Switching DC-DC converter, LDO) for IoT, extremely-low power and low-voltage applications. Generally, the ripple of power supply follows a rule of thumb (for example 1% of Vout)
(just for an example).
Nowadays, with the state-of-the-art...
I am still wondering why, for example, if we use R and current sink as 2 extremes, why don't we just use R with min and max values for checking stability?
Also, should I understand that with iload min, and max, we have to use both of R and curent sink for each case respectively?
That means...
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